Xilinx Supports Two Million Gate FPGAs, Advances Packaging Technology
San Jose, CA-based Xilinx has released the latest version of its Alliance Series software. The new software, designated version 2.1i, delivers a 50% reduction in compile times while delivering methodologies that support the design of two million gate Virtex field-programmable gate arrays (FPGAs).
Through close collaboration with its Alliance electronic design automation (EDA) partners, the new software provides improved synthesis capabilities. By offering these capabilities, engineers can infer architectural features such as delay locked loops (DLL) and block random-access memory (RAM) within the Alliance Series software package in order to achieve a more simplified design entry method while improving utilization. The synthesis feature coupled with fast compile times enables the productivity necessary to accomplish multiple design turns per day to meet the challenge of decreasing time to market.
Internet design
Continuing in the Silicon Xpresso initiative and leveraging the current functionality of the Internet, Xilinx has also enabled Internet team design (ITD) capabilities within version 2.1i of Alliance Series software. The ITD tool allows teams of designers to build high-density programmable logic designs over the Internet.
As Xilinx device densities approach two million system gates and beyond, engineers must coordinate multiple design modules from others in remote locations. The ITD tools use the Internet to deliver improved communication between all members of the design team, coordinate the different design source files, and integrate different design flows seen in today's typical FPGA design.
The ITD method creates a designer website that resides on the users' integral network. This website is a forms-based Web page where designers log-on and submit their design files to the project using their chosen Internet browser. Once submitted, the files are merged into a design project using ITD's design control system (DCS).
The DCS behaves as a Web-based revision management system that ensures that the various iterations of a design's modules are properly linked into the top-level design. Using the ITD tool, the design team leader can easily integrate the design modules and place-and-route the design using the standard Xilinx implementation tools included within the Xilinx Alliance Series software.
Once the design is placed and routed, detailed reports are issued to the IDT website for review by the design team. In this way, the team can brainstorm and collaborate on the creation of any additional iterations.
The Alliance Series 2.1i software provides architecture-specific device support for all Xilinx product families, including Spartan/XL, Virtex, XC4000X, XC4000XV, XC3100A/L, and XC5200 FPGAs, plus XC9000 complex programmable logic devices (CPLDs). The new software will be available in June for popular PC and workstation platforms and operating systems such as Windows 95 and Windows NT, Chinese, Korean, and Japanese Windows, Solaris, and HP-UX.
Pricing for the new Alliance Series software pricing starts at $95. Evaluation software are available for qualified users.
New packaging options
In addition to its latest Alliance Series software release, Xilinx has announced new packaging technology for its FPGA and CPLD products. According to the company, this new technology reduces board space and increases input/output (I/O) counts for customers.
Using the new technology, Xilinx has developed 144-ball and 280-ball, 0.8-mm pitch chip scale packages (CSPs) for its SpartanXL FPGA and XC9500 CPLD families. In addition, the company has launched 256-to-680-ball fine pitch ball-grid array (FBGA) for its Virtex FPGAs that features a 1-mm pitch.
For more information on the new Alliance Series software or new packages, contact Xilinx at 408-559-7778.