Together with Xilinx, Altera has been the other half of the two-party system driving the FPGA arms race forward for many years. Big headlines were made when it was recently announced that Intel would would buy Altera in a $6.7 billion cash deal. Among other things, Intel will be acquiring Altera's new Stratix 10 chip, a device some are calling(Opens in a new window) "the most significant step forward in high-end FPGAs."
The chip features the revolutionary HyperFlex core fabric architecture built on the Intel 14 nm Tri-Gate process. This equates to a 2X core performance gain over other high-performance FPGAs at up to 70% lower power. The Hyperflex design addresses some of the issues that come in to play at high GHz frequencies. The primary concern is minimizing the so-called propagation delay -- the time it takes a signal to travel from one register to the next. There are two components to propagation delay, the logic or gate delay, and the routing or wiring delay.
Normally, one might try to speed things up by widening the buses to move more things in parallel. The downside is that a much larger die is generally needed, and it also consumes more power. Instead, Altera focussed on the routing delay by simply adding more registers. The key is that their 'hyper-registers' can be associated not only with each routing segment on the chip, but also with the other amenities like DSP and embedded memory. Unlike general registers, hyper-registers also include the option to be bypassed.
On the design end -- not the chip design itself, but rather the design that the user burns into the chip -- this bypassing feature allows optimal register location to be automatically programmed in after the 'place-and-route' step. The place-and-route is typically what the designer does after creating the circuit (the set of logic elements together with the netlist connecting them), by popping the logic and connections into their desired places and pins on the chip.
Some other features(Opens in a new window) that caught our eye include the integrated quad-core 64 bit 1.5 GHz ARM Cortex-A53 hard processor system, and 10 TFLOPS of IEEE 754 compliant single precision floating point DSP. The heterogeneous 3D System-in-Package (SiP) integration also sounds cool, although I am not really sure what all that entails. It must be good, because with up to 5.5 million logic elements the chip claims itself to be the highest density highest density FPGA fabric available.
Clearly not business analysts, we have nonetheless noted that only a few companies have so far availed themselves of Intel’s 14nm process, with Altera being one of the majors. Apparently, Intel has indicated they will be integrating FPGAs into future Xeon products to add some processor customization capability. Gaining access to Altera's technology at a deeper level should definitely complement the FPGA packaging services that Intel already provides for customers.Tagged In
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