Intel (News - Alert) is releasing its “Haswell-EX” Xeon E7 v3 processors soon, tossing competitive fuel on the high-end server fire.
The Xeon E7 v3 processors were designed to work in the Brickland server platforms, which first debuted by using Haswell’s predecessor, Ivy Bridge processors, in February 2014. Brickland will eventually support the Broadwell and Skylake processors too, slated to appear in the next 12-18 months.
As website The Platform points out, “server makers and customers alike do not want the cost and complexity of changing sockets every one or two generations. They want to have a platform certified to support multiple generations of processors in a single socket type – in this case, Socket R1 – over a span of years that more closely matches the upgrade cycle of big iron.”
That’s also a way for Intel to optimize its innovation cycle. To wit: the Haswell generation of Xeons represents a “tock” of what Intel calls a ‘tick-tock method’ of upgrading its server processors.
With every "tick" cycle, Intel advances manufacturing process technology to advance Moore’s Law—the latest tick was the move to 22 nanometer chips. That was a typical increase in transistor density that enables new capabilities, higher performance levels and greater energy efficiency—all within a smaller, more capable version of the previous “tock” microarchitecture.
In server terms, the Intel introduction of the 22-nm Ivy Bridge generation of Xeons, including Xeon E3s for single socket-machines, Xeon E5s for two-socket and four-socket machines, and Xeon E7s for four-socket and larger machines, is representative of the tick.
In alternating “tock” cycles, Intel uses the previous tick cycle’s manufacturing process technologies to introduce new processor microarchitecture, which seeks to improve energy efficiency and performance as well as functionality and density of features such as hardware-supported video transcoding, encryption/decryption and other integrated capabilities.
The Haswell generation is just such a tock, and, notable among the improvements, the Haswell Xeon E7 chips will support more sophisticated power control for lower consumption—thus becoming an implementation of Moore’s Law advancement.
With the launch of the “Haswell-EX” Xeon E7 v3 processors, Intel is turning the heat up a little more on its competitors, who are making their cases for their Power and Sparc motors and the systems that use them.
The Haswell Xeon E7 v3 processors, which has 5.7 billion transistors and has a die area of 662 square millimeters, have 20 percent more cores and 20 percent more L3 cache than their predecessors, which “is enough to make it worthwhile for both server buyers and server sellers,” The Platform noted. “The important thing for big iron customers is that the new Xeon E7 v3 chips sport the Haswell cores. The changes in the microarchitecture continue to push the amount of work a core can do per clock cycle.”
The Haswell cores also have better branch prediction, deeper buffers, more table lookaside buffers, and more execution units. They also have QPI links that have a top speed of 9.6 gigatransfers per second, up from 8 GTpsec with the Ivy Bridge E7 QPI links.
Intel is already planning the next tock, which is a move to the 14-nanometer process. Broadwell is the silicon that’s expected to make use of that—and it’s already been rolled out on the Xeon D chip for microservers that Intel launched in March. Broadwell Xeon E5 processors are expected later this year, while sometime in the next twelve to sixteen months, Intel will roll the 14 nanometer process up to the Broadwell-EX.
Further on down the road, Skylake technology will represent a 10-nanometer process, starting with the low-end Xeon E3 servers.
Edited by Rory J. Thompson