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Three-level Discontinuous Space Vector Modulation at Low Switching Frequency [Sensors & Transducers (Canada)](Sensors & Transducers (Canada) Via Acquire Media NewsEdge) Abstract: The three-level discontinuous pulse-width modulation (DPWM) which can reduce switching frequency while restrain the switching loss of high power converters was proposed. Space-vector discontinuous modulation (SVDM) suitable for digital implement was also presented. Detailed analysis were given to verify the control performance of the two recommended SVDM methods and traditional space vector modulation (SVM) in switching loss and harmonic characteristic field. Three-level neutral-point-clamped (neutral-point-clamped, NPC) SVDM rectifiers were designed to evaluate their behavior in neutral-point potential control, robustness and static and dynamic response. The correctness and feasibility of the proposed control scheme are verified by the simulating and experimental tests. Copyright © 2014 IFSA Publishing, S. L. Keywords: Switching loss, Discontinuous modulation, Space vector control, Three-level NPC rectifier. (ProQuest: ... denotes formulae omitted.) 1. Introduction Switching loss of the power devices has become a serious problem, along with the wide application of the high power multilevel converters in the high performance and high power industrial field, e. g. mine hoisting, locomotive traction and metal rolling [1], In order to improve the converters output power, the switching frequency of semiconductors should be kept at low value, for IGBT or IGCT, usually lower than 500 Hz [2], Traditional continuous pulse-width modulation (CPWM), including space vector modulation (SVM), sinusoidal pulse-width modulation (SPWM), has a series of problems when the switching frequency is low, such as high harmonic distortion, bad stability and control performance, all of which could not meet the requirement of the control system. Discontinuous pulse-width modulation (DPWM) has power devices acting only on two phase at any time, while the device of third phase clamping at special level, so DPWM could reduce about 1/3 switch motion compared to the traditional CPWM. Besides, when the switching loss is the same, DPWM has more effective switch mode, and would decrease the filter capacity to reduce the electromagnetic interference (EMI) as well as the increase of power quality and power density [3]. Firstly, DPWM was used in three-phase two-level voltage-source-converter to reduce the switching loss and improve the efficiency. These years, deeply research has been carried out for the combination of DPWM and high power converters. In [4], the mathematical model of DPWM has been derived. In [5], it had been analyzed and proved that, compared to the CPWM, DPWM had a larger modulation range, high voltage gain and small harmonic distortion. Along with the development of the technology for the medium and high voltage converters, DPWM have been widely applied in the multilevel converters. Both the DPWM implementation in three-level and five-level has been analyzed in [6] and [7]. In [8] and [9], DPWM was used in the multi-phase motor and the active filter. However, most of the literature only focused on the DPWM study based on the zero-sequence voltage injection [10], rarely on the system comparison and performance analysis. According to above issues, in this paper, the implementation method of DPWM from three-level carrier modulation to space vector modulation has been firstly researched, and two kinds of improved three-level DPWM based on the space vector modulation would be analyzed and verified. And then, it took a comparison between the improved DPWM and SVM on the switching loss and the current harmonic characteristic when the switching frequency was low. Then, a widely used three-level neutral point clamped voltage-source PWM rectifier has been adopted as the test platform to evaluate their behavior in neutral-point potential control, static and dynamic response by the simulation and experimental results. 2. Three-level Discontinuous Space-vector Modulation Mechanism Traditional three-level 60° DPWM can be implemented by the three-level carrier pulse width modulation [12], which follows the two-level DPWM2 [11]. All of the modulation strategy of twolevel DPWM can be applied to the three-level. However, because of the additional neutral clamping point of the three-level topology, a new improved DPWM was proposed in [6]. Compared to the traditional three-level 60° DPWM, this kind of improved DPWM has the outputs not only be clamped on the minus or plus bus voltage, but the neutral point. Owing to the easy digital implementation of the space-vector modulation, the three-level DPWM would be achieved using the space vector in this paper that is called SVDM. The basic principle of three-level SVM is that, the reference voltage complex vector is synthesized by the three nearest space vectors in each switching period [13]. Short vectors can decide the direction of the neutral current iM, and here, we take the Ô+ and 8- to represent the duty period of the forward and reverse short vector. So, the controllable freedom factor of the SVM can be defined as: ... (1) The main purpose of the DPWM is to reduce the switching loss, so, it should be avoided that the power devices act on the peak (or near the peak) of each phase current. In order to decrease the switching times as much as possible, the switching order of seven-segment or nine-segment should be changed to five-segment. During one switching period, long vectors are put in the middle, while short vectors are in the beginning or the end. In this paper, we don't change the direction of the neutral current by the adjustment of the short vectors, but the neural current average is maintained to be zero during the whole fundamental period. The improved three-level DPWM achieved by the space vector was called as SVDMA in [6], whose space vector diagram is shown in Fig. 1, where, different color represents different clamp district of each phase. For example, when the reference voltage vector is in the area C, phase A would be clamped at the positive level. The difference between the SVDMA and DPWM2 is that, SVDMA moves the zero vector from origin to the vertex of the inner hexagon. The specific method: during the 0-60° area, when p-=l, switching order could be expressed as ... During the above switching period, two power devices of the lower bridge arm of phase A keep close all the time, and the phase voltage would be clamped at positive level. The number, location and the length of the clamp region all depend on the modulation index of the SVDMA. At the assumption of modulation index M= Fphase / (V^ / 2), where VPhase and Vdc are the phase voltage amplitude and the DC bus voltage respectively. When M<2/3, phase A would be clamped at zero. So, SVDMA is only suitable for the range of M>2/3. Simulations have been carried out by the MATLAB, and the waveforms are shown in Fig. 2. The average switching frequency of the power devices is 1 kHz, M=0.95, and, tTll and tT14 represent the duration time of the first and four device of phase A during one switching period. Another three-level discontinuous space vector modulation which has a better harmonic performance is called SVDMB, the extended application of DPWM3 [14]. Being different from the SVDMA, the switching loss of SVDMB doesn't change along with the modulation index, and the selection and the use interval of pare also different from the SVDMA. The space vector diagram for SVDMB is shown in Fig. 3. Taking the 0-60° region C shown in Fig. 3 for example, switching period is T and the switch sequence (beginning with short vector 0-) is ...|t=0(0-)-»(+")-K+0-) 11 = 1 /2T->(+0-)-»(+-) ->(0-)|t=T.... During this period, two power devices of the upper bridge arm of phase C keep close all the time, and the phase voltage would be clamped at negative level. The simulation waveforms are shown in Fig. 4. 3. Research on the Control Performance of Three-level SVDM 3.1. A Calculation of Switching Loss For the high power converters, the current harmonic distortion and the switching loss of power devices are the important factors to evaluate the performance of the modulation strategy. And the harmonic distortion can be evaluated by the HDF and THD, while the switching loss is related to the switching times and the load current. Generally, one of the limiting factors for the high power converters is the switching loss of the power devices. Design of the cooling system, efficiency of the heat dissipation system and the fever of the power devices, all of these determine the maximum power of the loss. It's inaccurate to evaluate the switching loss of the different discontinuous modulation strategy by the carrier frequency or the switching frequency, it's better to establish a more precise mathematical model to carry out some analysis and to take a calculation on the condition that, the thermal stress of devices is the same [15,16]. Normally, in order to utilize the converter capacity fully, the modulation index range of the three-level rectifier is Mg[2/3,2/^]. So, in this paper, the SVDMA, SVDMB and the SVM are only analyzed and compared in this range. The switching loss the whole fundamental period can be obtained by the integration of that for the single switch period pL. Considering the symmetry of the phase voltage, it has ... (2) where cop represents the sum of the turn-off and turnon loss during one switch cycle, kf stands for the constant related to the devices terminal voltage and the natural characteristic, f is the switching frequency, i is the phase current. And the switching loss of the whole fundamental period is ... (3) For SVM, pis always 0.5, and the switch state is continuous during the whole fundamental period [0, 2n\. So, taking the phase A for example, the total loss of SVM can be obtained according to the Fig. 5. ... (4) where Imax is the peak value of the phase current. The clamp region of SVDMA changes with the modulation index M, and the clamp region should be removed from the integration, so, the total switching loss becomes as ... (5) The clamp region of SVDMB is different with SVDMA's, it is independent on the M. Similarly, the total switching loss of SVDMB is ... (6) The relationship between the modulation index M and the switching loss PL for different modulation strategy is shown in Fig. 6, where the switching frequency and the phase current keep same and the switching loss of SVM is normalized as 1. In Fig. 6, it can be seen that, when M=1.15 and M=0.667, the switching loss of SVDMA is half and 0.866 times of the SVM's. During the range of M^0.667,1.15], the switching loss of SVDMB is 0.63 times of the SVM's. That is to say, with a same switching loss, the switching frequency of SVDMA can increase to the 1.732M times of the SVM's, while SVDMB's increase to 1.58 times of the SVM's. 3.2. Analysis of the Harmonic Characteristics From above analysis, it can be known that, on the condition of same switching loss, SVDM could select high switching frequency and have a better harmonic characteristic. However, harmonic components of the phase current are only related to the switching frequency, also the position and number of the short vectors in the whole fundamental period. The controlling factor of SVDM in single switch period keeps p-=0 or p-=l, alternately, which would increase the harmonic components of the phase current. In order to analyze the harmonic characteristics of SVDM in detail, models of the three-level NPC inverter with pure inductance load were established in the MATLAB/Simulink, and a comparative analysis has been carried out for the SVM, SVDMA and SVDMB. All of the signals were discrete and normalized and the switching frequency of each has been converted on the basis of same total switching loss. Sampling the harmonic distortion of the three phase current at different modulation index, and the current distortion obtained by the five times of curve fitting [17] are shown in Fig. 7, where the switching frequency is as low as 500 Hz. In Fig. 7, it can be known that, with a low switching frequency, the harmonic distortion of SVDMA increase along with the reduction of the modulation index, in the low index range, the distortion would higher than 5 %. For SVDMB, the distortion keeps smooth when M<0.85, and increases when M>0.8. The harmonic distortion of SVM is an approximately parabola and the minimum value comes at M=0.7. For the practical system, in order to utilize the converter capacity fully, the modulation index is usually a big value. From Fig. 7, when the index is high, the distortion of the SVDMA and SVDMB is similarly, while SVM's is bigger, which shows that the former two are suitable for the high index. 3.3. Performance Analysis of the Three-level NPC-SVDM Rectifier A three-level PWM rectifier platform, which can realize the unity power factor and a adjustable DClink, was established to analyze and verify the control effects of the SVDM, such as the neutral point balance, dynamic response and the robustness [18]. The parameters are: inductance on ac side L=10 mH, resistance on ac side R=0.01 Q, load resistance RLoad=130 Q, DC-link capacitance Cdc1=2000 pF and Cdc2=2400 pF. The simulation waveforms of SVDM (switching frequency f=500 Hz) are shown in Fig. 8, where, at T=0.2 s, the load becomes twice the original. From Fig. 8 (a) and Fig. 8 (b), it can be seen that, for SVDMB, the dynamic recovery time is about three fundamental periods, and the ±10 % fluctuation of the DC-link capacitance has no obvious influence on the control system with a neutral point voltage difference less than 10 V; also, it can realize the unity power factor control, and meet the control requirements of the three-level rectifier. From Fig. 8(c) and Fig. 8(d), we can know that, on the same condition, the asymmetric of the DC-link capacitance has a great influence on the control system of the SVDMA; besides, with a sudden load changing, there are some problems such as DC-link voltage ripple, phase current distortion and the increase of the neutral point voltage difference. So, for the three-level NPC-SVDM rectifier, SVDMB system has outstanding performance compared with SVDMA, because load changing and the fluctuation of the DC-link capacitance both could decline the control performance of the SVDMA system. 4. Experimental Results In order to verify the control performance of the SVDM, some related experiments have been carried out on the platform of the three-level NPC rectifier. Owing to the restriction of the experimental conditions, the research on the switching loss at different modulation haven't been taken temporarily, only the harmonic distortion was compared with the consideration of the harmonic characteristics and the control of neutral point potential. Taking SVDMB as the modulation strategy for the three-level NPC rectifier, and the experimental parameters are shown in Table 1. Fig. 9(a) shows the waveforms of phase A voltage and the modulation waveform for line voltage, which transmitted from DSP to FPGA, and displayed on the oscilloscope TDS1002B [19,20]. The switch pulses of the two power devices on the upper bridge arm of phase A are shown in Fig. 9(b), and from which, it can be seen that, in the 0-30° area, the position of clamp region is in the ±45° of the correspond peak and the switching frequency is 500 Hz. The experimental results are consistent with the theoretical analysis and the simulation. The current harmonic distortion obtained from the power quality analyzer Fluke43B, of SVM, SVDMB and SVDMA are shown in Fig. 10, where the switching frequency and the modulation index are the same. When f=500 Hz and M=l, the distortion of SVDMA is the smallest, SVDMB second, and SVM's is the large Fig. 11 shows the grid current and voltage at steady-state at f=500 Hz, with a smoothing waveforms and good degree of sinusoidal. In order to verify the dynamic performance of SVDMB, the experiments of the DC-link voltage mutation and the sudden load changing were carried out, and the results are shown in Fig. 12. In Fig. 12(a), when the given value of DC-link voltage changed suddenly, the response time of the voltage loop is about 200 ms, which could meet the dynamic requirement. And Fig. 12(b) is the dynamic response waveforms of the grid current when the load is twice of former, and the dynamic response time is approximate two switch periods, which verify the dynamic performance and the robustness of SVDMB. 5. Conclusions The switching loss of power devices and the harmonic characteristics are the key performance indexes of the high power converters. According to the low switching frequency, two kinds of SVDM have been analyzed and compared with the traditional SVM. And a three-level NPC-SVDM rectifier platform has been established to test the control performance of the different modulation strategy focusing on the neutral point control, the dynamic and steady response and the robustness. The simulation and experimental results show that, the advantage of SVDM with a low current distortion increases along with the reduction of the switching frequency. On the same conditions, the switching loss of SVDMA and SVDMB could be reduced to the 0.58 % and 0.63 % of the SVM's, while SVDMB acts better than SVDMA on the neutral point control and the robustness. For the three-level SVDM, some research on the space vector modulation, switching loss, harmonic characteristics and robustness analysis have been attempted. The advantages of SVDM are not only embodied in the control system of the three-level NPC rectifier, also can be transplanted to the motor system and other applications of the high power converters. According to the practical system, the dead-time compensation, narrow pulse elimination and design of the filters are the next research emphasis. Acknowledgements Project Supported by Xiamen Great Project of Fujian Province (51077124); Project of Education Department of Fujian Province (JA13234)(JB12188); Science and Technology Project of Fujian province (2012H0040). References [1]. H. Abu-Rub, J. Holtz, J. Rodriguez, et al, Mediumvoltage multilevel converters - state of the art, challenges, and requirements in industrial applications, IEEE Transactions on Industrial Electronics, Vol. 57, Issue 8,2010, pp. 2581-2596. [2]. A. Rathore, J. Holtz, T. Boiler, Synchronous optimal pulsewidth modulation for low switching frequency control of medium voltage multi-level inverters, IEEE Transactions on Industrial Electronics, Vol. 57, Issue 7,2010, pp. 2374-2381. [3]. Yu Fei, Zhang Xiaofeng, Li Huaishu, et al, A zero sequence offset time based low loss and high performance PWM control method, Automation of Electric Power Systems, Vol. 29, No. 2, 2005, pp. 39-44 (in Chinese). [4]. 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TMS320F28335/ F28334/ F28332/ F28235/ F28234/ F28232 digital signal controllers, Texas Instruments, Inc., Dallas, 2009. [20]. Tian Yun, Xu Wenbo, Hu Bin, Developer's guide of the Xinlinx ISE design suitelO.x FPGA, Posts and Telecom Press, Beijing, 2008, pp. 400-409. Ji Zhang, Tian-Xiang Chen, Yan-Qing Peng The School of Electrical Engineering and Automation, Xiamen University of Technology Xiamen, 361024, China Tel: +86-13799269537, fax: +86-05926291057 E-mail: [email protected] Received: 30 May 2014 /Accepted: 27 June 2014 /Published: 30 June 2014 (c) 2014 IFSA Publishing, S.L. |