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U.S. Patents Awarded to Inventors in Idaho (April 17)
[April 17, 2014]

U.S. Patents Awarded to Inventors in Idaho (April 17)


(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., April 17 -- The following federal patents were awarded to inventors in Idaho.

*** Micron Technology Assigned Patent for Insulative Material Supports ALEXANDRIA, Va., April 16 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,691,704) developed by two co-inventors for methods for "selectively etching insulative material supports relative to conductive material." The co-inventors are Kevin R. Shea, Boise, Idaho, and Thomas M. Graettinger, Boise, Idaho.



The patent application was filed on May 29, 2013 (13/904,828). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8691704.PN.&OS=PN/8691704&RS=PN/8691704 Written by Merly Lapig; edited by Karen Narag.

*** Battelle Energy Alliance Assigned Patent ALEXANDRIA, Va., April 16 -- Battelle Energy Alliance, Idaho Falls, Idaho, has been assigned a patent (8,691,525) developed by four co-inventors for methods of "combined bioprocessing and related microorganisms, thermophilic and/or acidophilic enzymes and nucleic acids encoding said enzymes." The co-inventors are David N. Thompson, Idaho Falls, Idaho, William A. Apel, Jackson, Wyo., Vicki S. Thompson, Idaho Falls, Idaho, and Thomas E. Ward, Pennsylvania Furnace, Pa.


The patent application was filed on June 21, 2013 (13/924,149). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8691525.PN.&OS=PN/8691525&RS=PN/8691525 Written by Merly Lapig; edited by Karen Narag.

*** Micron Technology Assigned Patent for Bimodal Disable Circuits ALEXANDRIA, Va., April 16 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,692,603) developed by five co-inventors for methods, apparatuses and circuits for "bimodal disable circuits." The co-inventors are Eric Booth, Boise, Idaho, Tyler J. Gomm, Boise, Idaho, Kallol Mazumder, Plano, Texas, Scott E. Smith, Plano, Texas, and John F. Schreck, Lucas, Texas.

The patent application was filed on Aug. 23, 2013 (13/975,100). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8692603.PN.&OS=PN/8692603&RS=PN/8692603 Written by Merly Lapig; edited by Karen Narag.

*** Micron Technology Assigned Patent for Memory Cell Access Devices ALEXANDRIA, Va., April 16 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,692,320) developed by four co-inventors for "recessed memory cell access devices and gate electrodes." The co-inventors are Jasper S. Gibbons, Boise, Idaho, Darren V. Young, Orem, Utah, Kunal R. Parekh, Boise, Idaho, and Casey Smith, Salt Lake City.

The patent application was filed on Oct. 18, 2011 (13/276,141). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8692320.PN.&OS=PN/8692320&RS=PN/8692320 Written by Merly Lapig; edited by Karen Narag.

*** Micron Technology Assigned Patent ALEXANDRIA, Va., April 16 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,691,656) developed by three co-inventors for methods of "forming an interconnect between a substrate bit line contact and a bit line in dynamic random access memory." The co-inventors are Brett W. Busch, Boise, Idaho, David K. Hwang, Boise, Idaho, and Daniel F. Gealy, Kuna, Idaho.

The patent application was filed on Sept. 7, 2011 (13/226,787). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8691656.PN.&OS=PN/8691656&RS=PN/8691656 Written by Merly Lapig; edited by Karen Narag.

*** Micron Technology Assigned Patent for Semiconductor Devices and Structures ALEXANDRIA, Va., April 16 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,692,305) developed by three co-inventors for "semiconductor devices and structures including at least partially formed container capacitors." The co-inventors are Brett Busch, Boise, Idaho, Kevin R. Shea, Boise, Idaho, and Thomas A. Figura, Boise, Idaho.

The patent application was filed on Nov. 1, 2011 (13/286,702). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8692305.PN.&OS=PN/8692305&RS=PN/8692305 Written by Merly Lapig; edited by Karen Narag.

*** Micron Technology Assigned Patent for NAND Memory Device Operation ALEXANDRIA, Va., April 16 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,694,860) developed by three co-inventors for a method and system for "operating a NAND memory device." The co-inventors are Theodore T. Pekny, Sunnyvale, Calif., Victor Y. Tsai, Palo Alto, Calif., and Peter S. Feeley, Boise, Idaho.

The patent application was filed on Jan. 7, 2013 (13/735,789). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8694860.PN.&OS=PN/8694860&RS=PN/8694860 Written by Merly Lapig; edited by Karen Narag.

*** Micron Technology Assigned Patent for Memory Cells ALEXANDRIA, Va., April 16 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,691,622) developed by two co-inventors for "memory cells and methods of forming memory cells." The co-inventors are John Smythe, Boise, Idaho, and Gurtej S. Sandhu, Boise, Idaho.

The patent application was filed on May 25, 2012 (13/480,610). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8691622.PN.&OS=PN/8691622&RS=PN/8691622 Written by Merly Lapig; edited by Karen Narag.

*** Micron Technology Assigned Patent for Electrical Limit Protection ALEXANDRIA, Va., April 16 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,693,148) developed by two co-inventors for integrated circuits, memories, protection circuits and methods "for protecting against an over-limit electrical condition at a node of an integrated circuit." The co-inventors are Michael Chaine, Boise, Idaho, and Xiaofeng Fan, Boise, Idaho.

The patent application was filed on Jan. 8, 2009 (12/350,831). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8693148.PN.&OS=PN/8693148&RS=PN/8693148 Written by Merly Lapig; edited by Karen Narag.

*** Micron Technology Assigned Patent for Memory Device Repair Apparatus ALEXANDRIA, Va., April 16 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,694,861) developed by two co-inventors for "memory device repair apparatus, systems, and methods." The co-inventors are Yutaka Ito, Tokyo, and Adrian J. Drexler, Meridian, Idaho.

The patent application was filed on Aug. 23, 2012 (13/593,217). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8694861.PN.&OS=PN/8694861&RS=PN/8694861 Written by Merly Lapig; edited by Karen Narag.

*** Micron Technology Assigned Patent for Couplings ALEXANDRIA, Va., April 16 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,693,231) developed by two co-inventors for "couplings within memory devices." The co-inventors are Akira Goda, Boise, Idaho, and Seiichi Aritome, Boise, Idaho.

The patent application was filed on June 13, 2012 (13/495,287). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8693231.PN.&OS=PN/8693231&RS=PN/8693231 Written by Merly Lapig; edited by Karen Narag.

*** Micron Technology Assigned Patent for Electronic Apparatus ALEXANDRIA, Va., April 16 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,692,568) developed by Tom Kinsley, Boise, Idaho, for an "electronic apparatus having integrated circuit temperature control." The patent application was filed on Oct. 3, 2011 (13/251,859). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8692568.PN.&OS=PN/8692568&RS=PN/8692568 Written by Merly Lapig; edited by Karen Narag.

*** Micron Technology Assigned Patent ALEXANDRIA, Va., April 16 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,691,015) developed by three co-inventors for a method and apparatus for "reducing halide-based contamination within deposited titanium-based thin films." The co-inventors are Garo J. Derderian, Boise, Idaho, Cem Basceri, Boise, Idaho, and Donald L. Westmoreland, Boise, Idaho.

The patent application was filed on April 8, 2013 (13/858,644). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8691015.PN.&OS=PN/8691015&RS=PN/8691015 Written by Merly Lapig; edited by Karen Narag.

*** Hewlett-Packard Development Assigned Patent for Toner Coverage Determination ALEXANDRIA, Va., April 17 -- Hewlett-Packard Development, Houston, has been assigned a patent (8,699,905) developed by four co-inventors for a toner coverage determination. The co-inventors are Sean Michael Collison, Meridian, Idaho, Brandi Michelle Pitta, Eagle, Idaho, Michael Joseph Martin, Boise, Idaho, and George Henry Kerby, Boise, Idaho.

The patent application was filed on June 7, 2012 (13/491,187). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,699,905.PN.&OS=PN/8,699,905&RS=PN/8,699,905 Written by Balkishan Dalai; edited by Jaya Anand.

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